1. Field of the Invention
The present invention relates to a semiconductor device employing a master slice layout in which a plurality of gate basic cells are formed previously on an LSI chip and then only a wiring design is added to construct desired logic circuits, and to a configuration of a semiconductor device and a layout design thereof capable of improving miniaturization of wiring patterns and integration density.
2. Description of the Prior Art
Various layout designs for a semiconductor integrated circuit may be prepared according to a scale of the integrated circuit and design approach. A fully-custom IC in which all layers are designed and manufactured for exclusive use is suited for the case where a large number of high performance ICs are to be manufactured. In contrast, a semicustom IC such as Application-Specific Integrated Circuits (ASICs) in which layers located below a wiring layer level are manufactured in advance and then only wiring layers are designed and manufactured is suited for the case where specific-application ICs are to be manufactured in a short term. In addition, the semicustom IC has such an advantage that design cost and production cost can be reduced. Such ASIC is also called a gate array or master slice layout. An example of the basic cell layout of the semiconductor integrated circuit of this type is shown in FIG. 1A.
The layout shown in FIG. 1A is composed of two gate basic cells 3a, 3b and substrate/contact regions 4a, 4b formed between the gate basic cells 3a, 3b. Respective gate cells 3a, 3b are composed of two source/drain diffusion regions 12, 14 and four gate polysilicon regions 11. In FIG. 1A, for example, if a two-input NAND gate is to be formed, the gate basic cells 3a, 3b comprising two n-MOS transistors 1a, 1b and two p-MOS transistors 2a, 2b respectively are arranged on the upper and lower sides to put the substrate/contact regions 4a, 4b therebetween, whereby constituting one block. In FIG. 1A, in a wiring channel grid serving as a basis when the wiring layers are designed, for instance, twelve lines X0 to X11 are specified in the X direction and seven lines Y0 to Y6 are specified in the Y direction.
In the layout of the gate basic cell in which the wiring channel grid is specified in this manner, as shown in a functional block layout pattern in FIG. 1B, for example, four-input (A, B, C, D) one-output (Z output) NAND gate is constructed by designing the layout of the wirings of the transistors 1a, 1b, 2a, 2b with the use of vertical metal wirings (VDD (higher potential) power supply wiring 5a, and VSS (lower potential) power supply wiring 5b) and a lateral metal wiring (connection wiring 6).
In the prior art, in the layout of the gate basic cell, pitches of the wiring channel grid are defined as a uniform value or defined uniformly in the X and Y directions respectively to make much account of its matching to layout CAD. Design values of the pitches of the wiring channel grid are defined according to a logical product of design rules in regions in which functional blocks are formed and wiring regions. Hence, the pitches of the wiring channel grid must be made narrower with the progress of miniaturization.
Meanwhile, in the technical field of the semiconductor integrated circuit, development of the LSI is entering the region called deep submicron generation or sub-quartermicron generation according to the progress of fine pattern techniques. In these generations, harmful influences due to miniaturization have become dominant. For example, it has become an issue that, according to miniaturization of the power supply metal wiring, generation of electromigration and/or source voltage drop of the transistors due to resistance of wiring material exert harmful influences upon an operation of the device. For this reason, the advance of miniaturization of the line width of the metal wiring has been slowed down after the middle of the 1980s compared to miniaturization of the gate length of the transistor. In addition, since contact resistance is increased because of miniaturization of the area of the contact hole, source voltage drop of the transistors has also been caused to thus exert harmful influences upon an operation speed of the device.
For the above reasons, it may be supposed that the line width of the power supply metal wiring is restricted to technological limits such as almost 0.3 to 0.5 .mu.m because of resistance value of material unless a room-temperature superconducting wiring is employed, and therefore it appears that miniaturization of the power supply metal wiring is at a critical stage. In particular, it has been said that miniaturization can be improved at most to the 2/3 extent of the present miniaturization even if Ag, Au, Cu, etc. whose resistance values are lower than Al being mainly used at present are employed. In other words, it is possible that wirings other than the power supply metal wiring can be further miniaturized, but it has become difficult to improve the integration density by using the conventional wiring channel grid having uniform pitches since the line width of the power supply metal wiring, etc. determine the design rule.
In the case that the pitches of the wiring channel grid are designed, two cases may be considered if classified broadly.
(i) One case is that only the design rule for the wiring process, i.e., wiring width and wiring interval, contact hole size and contact hole interval, via hole contact size and via hole contact interval in the multilevel wirings, etc. must be considered.
(ii) The other case is that design rules in fabrication stages prior to the wiring process must be considered. Namely, design rule for manufacturing process of the basic cell (basic cell process) in addition to the design rule for the wiring process must be considered to design the pitches of the wiring channel grid. In the following, early processes such as oxidation, CVD, ion implantation, RIE, etc. performed until the interlayer insulating film just under the bottom metal layer are formed, including patterning of the gate polysilicon of the basic cell, will be called "basic cell process". And the process after forming the interlayer insulating film, such as opening the contact holes in the interlayer insulating film and patterning the wiring layers will be called wiring process".
In the layout of the gate basic cell shown in FIG. 1A, only the design rule for the wiring process should be regarded in order to define pitches of the lines X1-X2-X3-X4, X7-X8-X9-X10 constituting the wiring channel grid. This corresponds to the case (i). In contrast, the design rules for contact margin allocated to the polysilicon regions 11, intervals between the polysilicon regions 11 and the source/drain regions 12, 14, and contact margin allocated to the source/drain regions 12, 14 should also be regarded-in order to define the pitches of the lines X0-X1, X4-X5, X6-X7, X10-X11 constituting the wiring channel grid. This corresponds to the case (ii). Similarly, the design rules for contact margin allocated to the polysilicon regions 11 and intervals between the polysilicon regions 11 should be regarded in order to define the pitches of the lines X5-X6, X11-X0 constituting the wiring channel grid. Further, in order to define the pitches of two sets of lines Y0-Y1-Y2, Y4-Y5-Y6, the design rule for contact margin allocated to the gate polysilicon regions 11 or intervals between the contact holes for the source/drain regions 12, 14 and the narrowest portion of the polysilicon region defining a gate length of the MOSFET should be regarded in addition to the design rule for the wiring process. In order to define the pitches of a set of lines Y2-Y3-Y4, the design rule for intervals between the source/drain regions 12, 14 and the substrate/contact regions 4a, 4b in addition to the design rule for the wiring process should be regarded. Still further, in order to define the pitches of a set of lines Y6-Y0 with taking the wiring channel grid Y0 in the adjacent block into account, the design rule for intervals between respective source/drain regions 14, 12 in the adjacent block in addition to the design rule for the wiring process should be regarded. These correspond to the above case (ii).
In general, the design rule for the basic cell process is hard to be miniaturized compared to the design rule for the wiring process because the separation between the gate polysilicon regions, contact margin, etc. must be taken in account. In other words, the pitches of plural sets of vertical lines X0-X1, X4-X5, X5-X6, X6-X7, X10-X11, X11-X0, and the pitches of lateral lines intersecting with these vertical lines and constituting the wiring channel grid are prescribed by the design rule for the basic cell process. And these pitches must be designed wider than the pitches of two sets of lines X1-X2-X3-X4, X7-X8-X9-X10 prescribed only by the design rules for the wiring process. Hence, if the pitches of the wiring channel grid are defined uniformly, the design rule should be indispensably defined based on the largest pitch of the wiring channel grid.
In the current semiconductor manufacturing technology, a difference between the design rule for the wiring process and the design rule for the basic cell process becomes conspicuous. More particularly, the pitches of two sets of lines X1-X2-X3-X4, X7-X8-X9-X10 constituting the wiring channel grid can be made narrow, nevertheless the pitches of two sets of lines Y0-Y1-Y2, Y4-Y5-Y6, to which the most severe design rule is applied, cannot be made narrow.
After all, as the pitches of the wiring channel grid are defined uniformly, the pitches of two sets of lines X1-X2-X3-X4, X7-X8-X9-X10 constituting the wiring channel grid are still maintained large as they are, whereby preventing an improvement of the integration density.
As explained earlier, in the prior art wherein the pitches of the wiring channel grid are set uniformly, there is the problem that the difference between the design rule for the wiring process and the design rule for the basic cell process has become remarkable so that the integration density has not been able to enhanced. Except for the problem attributable to the difference between the design rules, the power supply wirings and the large current signal wirings have also to be made narrow if the pitches of the wiring channel grid are uniformly made narrow.
Therefore, such problems have arisen that source voltage drop due to the wiring resistance, wiring defect caused by electromigration, etc. occur and disadvantages such as malfunction, reduction in operation speed, etc. are caused.